Summary written by USA Jobs 24 from Broadcom's advert and our data on 17,030 current US jobs. How we check every job
At a glance
Broadcom is hiring a Physical Design Engineer in San Jose, CA. It is a full-time role in Hardware & Semiconductors, asking for at least 2 years of experience, first listed on November 1. The description mentions Python and Ruby. Broadcom has 99 other openings in the US, 33 of them in San Jose, CA. Across all employers on USA Jobs 24 there are 60 Hardware & Chips openings in San Jose, CA today; the typical one asks for 8 years and advertises about $195,000 a year at the midpoint.
How the pay compares
Broadcom has not published pay for this job, or we could not find it in the advert. Of the 176 hardware & chips jobs in California on USA Jobs 24, 50% show pay, and the typical yearly midpoint among them is $197,000. That gives you a fair starting point when the subject comes up. California has a pay transparency law that requires most employers to give a pay range for jobs there, so it is reasonable to ask the recruiter for it.
Skills in this advert
How often each skill named in this advert appears across the 290 hardware & chips jobs we list today. Python is the most widely requested (38% of jobs), while Ruby is the least common (1%). Widely requested skills are what employers expect as a baseline; rarer ones show what is special about this job.
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Before you apply
- Check it is still open. We found this job on Broadcom's Workday site on November 1 and checked it again November 4, 5:17 AM ET. When an employer takes a job down, we remove it at our next daily update.
- Check the location works for you. This role is based in San Jose, CA. If you would need to move, ask whether relocation help is offered.
- Match the experience. The advert asks for at least 2 years of experience. If you are a little short, a close match on the skills in the advert can still win an interview.
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About hiring at Broadcom
Broadcom has 100 openings on USA Jobs 24 today across 10 states. Most are in software & IT (48), hardware & chips (31) and product & design (6). The biggest locations are San Jose, CA (34), Fort Collins-, CO (27) and Plano, TX (12). 6% of them are remote, 2% are open to entry-level candidates and 4% show pay. We collect Broadcom's jobs every day straight from its own careers system (Workday), never from job boards or agencies.
The employer's advert
This is Broadcom's own description of the job, copied word for word from its careers site. We have not edited it.
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Job Description:
Physical Design Engineer (New College Grad) — ASIC Products Division (APD)
Location: San Jose, CA
Position Type: Full-Time
Who We Are — Physical Design Team in APD
Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders—to co-design and manufacture complex, custom ASICs that power the modern digital backbone.
The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm/A14 nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success.
What Defines Our Physical Design Team
- Pioneering First-Pass Silicon in 3nm/2nm: Our team consistently pushes the boundary of physics, taking the largest and most complex die sizes from floorplan to tapeout on leading-edge foundry nodes (N7, N5, N3, and N2).
- Record-Breaking Scale & Complexity: We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors, multi-gigahertz clock frequencies, and dense multi-die 2.5D/3D integration (CoWoS, HBM3/4, chiplet architectures).
- Methodology & Flow Leadership: We develop and maintain cutting-edge in-house (AI Driven) automation and methodology across different EDA tools, setting the benchmark for signoff quality and turn-around-time (TAT).
About the Role
Broadcom’s ASIC Products Division (APD) is looking for a motivated Physical Design Engineer (NCG) to join our Physical Design team. In this role, you will work alongside experienced engineers in executing the implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will gain hands-on experience in complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14).
Key Responsibilities
- Participate in block-level floorplanning, and run placement and route (P&R) flows using industry-standard EDA tools.
- Perform Static Timing Analysis (STA), debug timing paths, and execute ECOs for timing closure.
- Run Physical Verification checks (DRC, LVS, ERC, Antenna) and resolve signoff violations.
- Analyze IR drop and electromigration (EM) to ensure power grid integrity.
- Develop and maintain automated scripts (TCL, Python, Ruby) to enhance flow efficiency and productivity
Basic Qualifications
- Education: Bachelor's Degree in Electrical Engineering, Computer Engineering + 2yrs of experience or Master’s degree in Electrical Engineering, Computer Engineering (Graduation date within the past 12 months).
- Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
- Familiarity with static timing analysis (STA) concepts, clocking, and setup/hold timing.
- Hands-on coursework, lab experience, or academic projects using EDA design tools (Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools).
- Proficient in scripting languages such as TCL, Python, Ruby, or Bash.
Preferred Qualifications
- Prior internship or research experience in ASIC physical design, synthesis, or physical verification.
- Basic understanding of Design for Testability (DFT), low-power intent (UPF/CPF), and FinFET technologies.
- Excellent problem-solving, debugging, and analytical skills.
Work Authorization / Eligibility Requirements
- Legal authorization to work in the U.S. is required
Compensation and Benefits
The annual base salary range for this position is USD 82,500.00 To USD 132,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
USA Jobs 24 copied this listing from Broadcom's official careers site on November 1, 2026 and checked it again November 4, 5:17 AM ET. Broadcom will never ask you to pay to apply or to buy equipment with a check they send you. If anyone does, it is a scam.
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