# AI/ML Silicon Accelerator Memory Architect

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Job Description:

### Memory Subsystems and Low-Power Data Transport

**Level:** Principal Architect/Distinguished Architect

**Function:** Silicon Architecture — AI/ML Accelerators

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## The Role

You will define the end-to-end memory *and* data transport architecture for our

accelerators — from the memory technology we bet on, through the controller, on-die network,

and DMA engines, all the way into the scratchpads feeding the compute blocks. This is not a

"pick the DRAM generation" role. It is ownership of the whole data path across multiple

silicon generations, including the performance-versus-power analysis that decides major

trade-offs and the co-architecture with internal teams and external memory/IP vendors.

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## What You'll Own

**Memory architecture and roadmap.** Multi-generation memory strategy across the portfolio —

HBM, LPDDR/GDDR/DDR, on-die SRAM hierarchies and scratchpads.

Capacity, bandwidth, and latency requirements derived from real AI workloads

(model size, KV-cache growth, prefill versus decode, MoE sparsity). Memory controller and

cache/scratchpad microarchitecture: scheduling, address mapping, QoS across compute, DMA,

and host traffic.

**Data transport and energy-efficient movement.** The complete path from memory to the MACs:

on-die interconnect (topology, flow control, deadlock avoidance, QoS under mixed traffic),

and the DMA, gather/scatter, layout-transform, and multicast engines that make it usable.

You own the pJ/bit budget as a first-class constraint.

**Modeling and silicon realization.** Analytical and simulation-based models that make

architectural calls with quantified confidence.

## Minimum Qualifications

- MSEE/MSCE or PhD in EE, CE, CS, or related field, or equivalent demonstrated

architectural impact.

- 18+ years in ASIC/SoC architecture focused on memory systems and data movement for HPC or

AI. Deep knowledge of memory subsystems: HBM, DDR/LPDDR/GDDR, controller architecture, cache

coherency and memory consistency models, tiered and pooled memory.

- Demonstrated ownership of a data movement architecture — on-die interconnect, DMA/copy

engines, buffer hierarchies, and the dataflow connecting them to compute — including what

each protocol (NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe) actually costs in latency, area, and power.

- Strong performance modeling and system-level simulation background; first-principles

command of latency, throughput, utilization, and scalability.

Compensation and Benefits

The annual base salary range for this position is USD 200,000.00 To USD 320,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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