Sr. Staff CAD- ASIC Design Verification Agentic Workflow

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation Agentic design verification workflow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.

What You Can Expect

We are seeking a highly innovative engineer to lead the development of next-generation Agentic AI workflows for Front-End Engineering. This role will focus on:

• Develop and deploy agentic workflows for ASIC verification activities.
• Automate regression analysis, failure triage, root-cause identification, and coverage closure.
• Build AI agents that interact with EDA tools, simulation environments, and verification databases.
• Integrate LLM-based assistants into verification flows.
• Develop workflows for: Test generation Assertion generation UVM code creation Bug analysis Coverage improvement recommendations Documentation generation
• Collaborate with design, DV, CAD, and methodology teams.
• Measure and improve verification productivity through AI-driven automation.
• Develop scalable infrastructure for agent orchestration and multi-agent collaboration.

What We're Looking For

BS/MS in Electrical Engineering, Computer Engineering, or related field.

4+ years of ASIC Design Verification experience:

• Strong expertise in: SystemVerilog UVM Assertions (SVA) Functional Coverage Constrained-random verification
• Experience with: Simulation-based verification Formal verification Emulation/FPGA prototyping
• Deep understanding of SoC/IP verification methodologies.

AI Skills:

• Experience with: LLMs Agent frameworks, prompt engineering AI workflow orchestration
• Understanding of: Multi-agent systems Autonomous planning and execution Tool calling and function orchestration

Experience with industry-standard tools such as:

• VCS/Verdi; Xcelium/Jasper, Siemens Questa
• Coverage and regression management tools
• Scripting language experience.

Expected Base Pay Range (USD)

127,630 - 191,200, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.


This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.


Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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